A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework
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چکیده
Article / Book Information 論題(和文) Title(English) A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework 著者(和文) 小平 行秀, 高橋 篤司 Authors(English) Yukihide Kohira, Atsushi Takahashi 出典(和文) , Vol. E91-A, No. 10, pp. 3030-3037 Citation(English) IEICE Trans. Fundamentals, Vol. E91-A, No. 10, pp. 3030-3037 発行日 / Pub. date 2008, 10 URL http://search.ieice.org/
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ورودعنوان ژورنال:
- IEICE Transactions
دوره 91-A شماره
صفحات -
تاریخ انتشار 2008